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| a FEATURES Complete Dual Matching ADC Low Power Dissipation: 225 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V Differential Nonlinearity Error: 0.1 LSB On-Chip Analog Input Buffers On-Chip Reference Signal-to-Noise Ratio: 49.2 dB Over Seven Effective Bits Spurious-Free Dynamic Range: -65 dB No Missing Codes Guaranteed 28-Lead SSOP IINA IINB IREFB IREFT QREFB QREFT VREF REFSENSE QINB QINA Dual Channel 8-Bit Resolution CMOS ADC AD9281 FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CLOCK DVDD DVSS "I" ADC REFERENCE BUFFER ASYNCHRONOUS MULTIPLEXER 1V CHIP SELECT THREESTATE OUTPUT BUFFER DATA 8 BITS I REGISTER AD9281 SLEEP SELECT "Q" ADC Q REGISTER PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9281 is a complete dual channel, 28 MSPS, 8-bit CMOS ADC. The AD9281 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 28 MHz sampling rate and wide input bandwidth will cover both narrowband and spread-spectrum channels. The AD9281 integrates two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers. Each ADC incorporates a simultaneous sampling sample-andhold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applications. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. The outputs of the ADCs are ported to a multiplexed digital output buffer. The AD9281 is manufactured on an advanced low cost CMOS process, operates from a single supply from 2.7 V to 5.5 V, and consumes 225 mW of power (on 3 V supply). The AD9281 input structure accepts either single-ended or differential signals, providing excellent dynamic performance up to and beyond 14 MHz Nyquist input frequencies. 1. Dual 8-Bit, 28 MSPS ADC A pair of high performance 28 MSPS ADCs that are optimized for spurious free dynamic performance are provided for encoding of I and Q or diversity channel information. 2. Low Power Complete CMOS Dual ADC function consumes a low 225 mW on a single supply (on 3 V supply). The AD9281 operates on supply voltages from 2.7 V to 5.5 V. 3. On-Chip Voltage Reference The AD9281 includes an on-chip compensated bandgap voltage reference pin programmable for 1 V or 2 V. 4. On-chip analog input buffers eliminate the need for external op amps in most applications. 5. Single 8-Bit Digital Output Bus The AD9281 ADC outputs are interleaved onto a single output bus saving board space and digital pin count. 6. Small Package The AD9281 offers the complete integrated function in a compact 28-lead SSOP package. 7. Product Family The AD9281 dual ADC is pin compatible with a dual 10-bit ADC (AD9201). REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD9281-SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Differential Nonlinearity (SE)1 Integral Nonlinearity (SE)1 Zero-Scale Error, Offset Error Full-Scale Error, Gain Error Gain Match Offset Match ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Aperture Delay Match Input Bandwidth (-3 dB) Small Signal (-20 dB) Full Power (0 dB) INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Output Voltage Tolerance (2 V Mode) Load Regulation (1 V Mode) Load Regulation (2 V Mode) POWER SUPPLY Operating Voltage Supply Current Power Consumption Power-Down Power Supply Rejection DYNAMIC PERFORMANCE2 Signal-to-Noise and Distortion f = 3.58 MHz f = 14 MHz Signal-to-Noise f = 3.58 MHz f = 14 MHz Total Harmonic Distortion f = 3.58 MHz f = 14 MHz Spurious Free Dynamic Range f = 3.58 MHz f = 14 MHz Two-Tone Intermodulation Distortion3 Differential Phase Differential Gain Crosstalk Rejection FS DNL INL DNL INL EZS EFS (AVDD = +3 V, DVDD = +3 V, FSAMPLE = 28 MSPS, VREF = 2 V, INB = 0.5 V, TMIN to TMAX unless otherwise noted) Min Typ 8 28 0.1 0.25 0.2 0.3 1 1.2 0.2 1.2 -0.5 Max Units Bits MHz LSB LSB LSB LSB % FS % FS LSB LSB V pF ns ps ps MHz MHz V mV V mV mV mV V V mA mA mW mW % FS REFSENSE = VREF REFSENSE = GND 1 mA Load Current 1 mA Load Current (32 MHz at +25C) REFT = 1.0 V, REFB = 0.0 V REFT = 1.0 V, REFB = 0.0 V Condition Symbol 1.0 1.5 3.2 5.4 AIN CIN tAP tAJ BW AVDD/2 2 4 2 2 240 245 VREF VREF VREF 1 10 2 15 10 15 2.7 2.7 3 3 75 0.1 225 16 0.15 35 AVDD DVDD IAVDD IDVDD PD PSR SINAD 5.5 5.5 260 0.75 STBY = AVDD, Clock Low 46.4 SNR 47.8 THD 49.1 48 49.2 48.5 -67.5 -60 -49.5 dB dB dB dB dB dB dB dB dB Degree % dB SFDR 49.6 IMD DP DG 65 56 -58 0.2 0.08 -62 f = 44.9 MHz and 45.52 MHz NTSC 40 IRE Mod Ramp FS = 14.3 MHz -2- REV. E AD9281 Parameter DYNAMIC PERFORMANCE (SE) Signal-to-Noise and Distortion f = 3.58 MHz Signal-to-Noise f = 3.58 MHz Total Harmonic Distortion f = 3.58 MHz Spurious Free Dynamic Range f = 3.58 MHz DIGITAL INPUTS High Input Voltage Low Input Voltage DC Leakage Current Input Capacitance LOGIC OUTPUT (with DVDD = 3 V) High Level Output Voltage (IOH = 50 A) Low Level Output Voltage (IOL = 1.5 mA) LOGIC OUTPUT (with DVDD = 5 V) High Level Output Voltage (IOH = 50 A) Low Level Output Voltage (IOL = 1.5 mA) Data Valid Delay MUX Select Delay Data Enable Delay Data High-Z Delay CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency NOTES 1 SE is single ended input, REFT = 1.5 V, REFB = -0.5 V. 2 AIN differential 2 V p-p, REFT = 1.5 V, REFB = -0.5 V. 3 IMD referred to larger of two input signals. Specifications subject to change without notice. 1 Symbol SINAD Min Typ Max Units Condition 47.2 SNR 48 THD -55 SFDR -58 VIH VIL IIN CIN 2.4 6 2 0.3 dB dB dB dB V V A pF VOH VOL 2.88 0.095 V V VOH VOL tOD tMD tED tDHZ tCH tCL 16.9 16.9 4.5 0.4 11 7 13 13 V V ns ns ns ns ns ns Cycles CL = 20 pF. Output Level to 90% of Final Value 3.0 tOD CLOCK INPUT ADC SAMPLE #1 ADC SAMPLE #2 ADC SAMPLE #3 ADC SAMPLE #4 ADC SAMPLE #5 SELECT INPUT Q CHANNEL OUTPUT ENABLED t MD I CHANNEL OUTPUT ENABLED SAMPLE #1 Q CHANNEL OUTPUT SAMPLE #2 Q CHANNEL OUTPUT SAMPLE #1-1 Q CHANNEL OUTPUT DATA OUTPUT SAMPLE #1-3 Q CHANNEL OUTPUT SAMPLE #1-2 Q CHANNEL OUTPUT SAMPLE #1-1 I CHANNEL OUTPUT SAMPLE #1 I CHANNEL OUTPUT Figure 1. ADC Timing REV. E -3- AD9281 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Parameter With Respect to Pin Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3 -65 Max +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 +300 Units V V V V V V V V V V C C C No. 1 2 3 4 5 6 7 8 9 10 11 12 Name DVSS DVDD NC NC D0 D1 D2 D3 D4 D5 D6 D7 Description Digital Ground Digital Supply Not Connected Not Connected Bit 0 (LSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (MSB) AVDD AVSS DVDD DVSS AVSS DVSS AVDD DVDD CLK AVSS Digital Outputs DVSS AINA, AINB AVSS VREF AVSS REFSENSE AVSS REFT, REFB AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SELECT CLOCK SLEEP INA-I INB-I REFT-I REFB-I AVSS REFSENSE VREF AVDD REFB-Q REFT-Q INB-Q INA-Q CHIP-SELECT Hi I Channel Out, Lo Q Channel Out Clock Hi Power Down, Lo Normal Operation I Channel, A Input I Channel, B Input Top Reference Decoupling, I Channel Bottom Reference Decoupling, I Channel Analog Ground Reference Select Internal Reference Output Analog Supply Bottom Reference Decoupling, Q Channel Top Reference Decoupling, Q Channel Q Channel B Input Q Channel A Input Hi-High Impedance, Lo-Normal Operation ORDERING GUIDE Model Temperature Range Package Description Package Options* AD9281ARS -40C to +85C AD9281-EB *RS = Shrink Small Outline. 28-Lead SSOP RS-28 Evaluation Board PIN CONFIGURATION DVSS DVDD NC NC (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 SELECT CLOCK NC = NO CONNECT CHIP-SELECT INA-Q INB-Q REFT-Q AD9281 TOP VIEW (Not to Scale) REFB-Q AVDD VREF REFSENSE AVSS REFB-I REFT-I INB-I INA-I SLEEP DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale." The point used as "zero" occurs 1/2 LSB before the first code transition. "Full scale" is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9281 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. E AD9281 AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS DRVSS AVSS AVSS AVSS AVSS AVSS a. D0-D9 AVDD AVDD REFBS b. Three-State Standby AVDD AVDD c. CLK AVDD IN AVSS AVDD AVSS AVSS REFBF AVSS AVSS AVSS d. INA, INB e. Reference f. REFSENSE g. VREF Figure 2. Equivalent Circuits OFFSET ERROR The first transition should occur at a level 1 LSB above "zero." Offset is defined as the deviation of the actual first code transition from that point. OFFSET MATCH scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. GAIN MATCH The change in gain error between I and Q channels. PIPELINE DELAY (LATENCY) The change in offset error between I and Q channels. EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD - 1.76)/6.02 It is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. TOTAL HARMONIC DISTORTION (THD) The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising clock edge. MUX SELECT DELAY The delay between the change in SELECT pin data level and valid data on output pins. POWER SUPPLY REJECTION The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. APERTURE JITTER THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. SIGNAL-TO-NOISE RATIO (SNR) Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. APERTURE DELAY SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. SPURIOUS FREE DYNAMIC RANGE (SFDR) Aperture delay is a measure of the Sample-and-Hold Amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO The difference in dB between the rms amplitude of the input signal and the peak spurious signal. GAIN ERROR The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full REV. E S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. -5- AD9281-Typical Characteristic Curves (AVDD = +3 V, DVDD = +3 V, FS = 28 MHz (50% duty cycle), 2 V input span from -0.5 V to +1.5 V, 2 V internal reference unless otherwise noted) 1 55 50 -0.5dB 45 -6dB 0 SNR - dB LSB 40 35 30 -20dB -1 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 CODE OFFSET 25 1.0E+05 1.0E+06 1.0E+07 INPUT FREQUENCY - Hz 1.0E+08 Figure 3. Typical INL Figure 6. SNR vs. Input Frequency 1 55 50 -0.5dB 45 SNR - dB LSB -6dB 0 40 35 30 -20dB -1 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 CODE OFFSET 25 1.0E+05 1.0E+06 1.0E+07 INPUT FREQUENCY - Hz 1.0E+08 Figure 4. Typical DNL Figure 7. SINAD vs. Input Frequency 1.00 0.80 0.60 -30 -35 -40 -20dB 0.40 THD - dB 0.20 -45 -50 -55 -60 -6dB IB - nA 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 -1.0 -0.5 0 0.5 1.0 INPUT VOLTAGE - Volts 1.5 2.0 -65 -0.5dB -70 1.0E+05 1.0E+06 1.0E+07 INPUT FREQUENCY - Hz 1.0E+08 Figure 5. Input Bias Current vs. Input Voltage Figure 8. THD vs. Input Frequency -6- REV. E AD9281 70 65 60 55 1.00E+07 1.20E+07 10000000 8.00E+06 THD - dB 50 HITS 45 40 35 30 25 4.00E+06 6.00E+06 2.00E+06 12050 N-1 N CODE 800 N+1 20 1.00E+06 0.00E+00 1.00E+07 CLOCK FREQUENCY - Hz 1.00E+08 Figure 9. THD vs. Clock Frequency Figure 12. Grounded Input Histogram 1.013 0 -3 1.012 -6 AMPLITUDE - dB -9 -12 -15 -18 -21 -24 VREF - Volts 1.011 1.010 1.009 1.008 -40 -20 0 20 40 60 TEMPERATURE - C 80 100 -27 1.00E+06 1.00E+07 1.00E+08 INPUT FREQUENCY - Hz 1.00E+09 Figure 10. Voltage Reference Error vs. Temperature Figure 13. Full Power Bandwidth 240 235 50 -0.5dB 45 -6dB POWER CONSUMPTION - mW 230 225 220 215 210 205 200 195 190 185 0 4 8 12 16 20 24 CLOCK FREQUENCY - MHz 28 32 SNR - dB 40 35 30 -20dB 25 1.00E+05 1.00E+06 1.00E+07 INPUT FREQUENCY - Hz 1.00E+08 Figure 11. Power Consumption vs. Clock Frequency Figure 14. SNR vs. Input Frequency (Single-Ended) REV. E -7- AD9281 10.0 0.0 -10.0 -20.0 -30.0 FUND converter to readily accommodate either single-ended or differential input signals. This differential structure makes the part capable of accommodating a wide range of input signals. The AD9281 also includes an on-chip bandgap reference and reference buffer. The reference buffer shifts the ground-referred reference to levels more suitable for use by the internal circuits of the converter. Both converters share the same reference and reference buffer. This scheme provides for the best possible gain match between the converters while simultaneously minimizing the channel-to-channel crosstalk. Each A/D converter has its own output latch, which updates on the rising edge of the input clock. A logic multiplexer, controlled through the SELECT pin, determines which channel is passed to the digital output pins. The output drivers have their own supply, allowing the part to be interfaced to a variety of logic families. The outputs can be placed in a high impedance state using the CHIP SELECT pin. The AD9281 has great flexibility in its supply voltage. The analog and digital supplies may be operated from 2.7 V to 5.5 V, independently of one another. ANALOG INPUT SNR - dB -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 2ND 9TH 3RD 8TH 4TH 7TH 5TH 6TH -100.0 -110.0 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6 Figure 15a. Simultaneous Operation of I and Q Channels 10.0 0.0 -10.0 -20.0 -30.0 FUND SNR - dB -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 2ND 3RD 4TH 5TH 6TH 7TH 8TH -100.0 -110.0 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6 Figure 16 shows an equivalent circuit structure for the analog input of one of the A/D converters. PMOS source-followers buffer the analog input pins from the charge kickback problems normally associated with switched capacitor ADC input structures. This produces a very high input impedance on the part, allowing it to be effectively driven from high impedance sources. This means that the AD9281 could even be driven directly by a passive antialias filter. Figure 15b. Simultaneous Operation of I and Q Channels IINA BUFFER ADC CORE +FS LIMIT IINB BUFFER +FS LIMIT = VREF +VREF/2 -FS LIMIT = VREF -VREF/2 -FS LIMIT THEORY OF OPERATION OUTPUT WORD SHA The AD9281 integrates two A/D converters, two analog input buffers, an internal reference and reference buffer, and an output multiplexer. For clarity, this data sheet refers to the two converters as "I" and "Q." The two A/D converters simultaneously sample their respective inputs on the rising edge of the input clock. The two converters distribute the conversion operation over several smaller A/D sub-blocks, refining the conversion with progressively higher accuracy as it passes the result from stage to stage. As a consequence of the distributed conversion, each converter requires a small fraction of the 256 comparators used in a traditional flash-type 8-bit ADC. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the following stages continue to process previous samples. This results in a "pipeline processing" latency of three clock periods between when an input sample is taken and when the corresponding ADC output is updated into the output registers. The AD9281 integrates input buffer amplifiers to drive the analog inputs of the converters. In most applications, these input amplifiers eliminate the need for external op amps for the input signals. The input structure is fully differential, but the SHA common-mode response has been designed to allow the VREF Figure 16. Equivalent Circuit for AD9281 Analog Inputs The source followers inside the buffers also provide a level-shift function of approximately 1 V, allowing the AD9281 to accept inputs at or below ground. One consequence of this structure is that distortion will result if the analog input comes within 1.4 V of the positive supply. For optimum high frequency distortion performance, the analog input signal should be centered according to Figure 27. The capacitance load of the analog input pin is 4 pF to the analog supplies (AVSS, AVDD). Full-scale setpoints may be calculated according to the following algorithm (VREF may be internally or externally generated): -FS = VREF - (VREF/2) +FS = VREF + (VREF/2) VSPAN = VREF -8- REV. E AD9281 The AD9281 can accommodate a variety of input spans between 1 V and 2 V. For spans of less than 1 V, expect a proportionate degradation in SNR. Use of a 2 V span will provide the best noise performance. 1 V spans will provide lower distortion when using a 3 V analog supply. Users wishing to run with larger full-scales are encouraged to use a 5 V analog supply (AVDD). Single-Ended Inputs: For single-ended input signals, the signal is applied to one input pin and the other input pin is tied to a midscale voltage. This midscale voltage defines the center of the full-scale span for the input signal. EXAMPLE: For a single-ended input range from 0 V to 1 V applied to IINA, we would configure the converter for a 1 V reference (see Figure 17) and apply 0.5 V to IINB. 1V 0V INPUT MIDSCALE VOLTAGE = 0.5V (1V) IINA I OR QREFT 0.1 F IINB 10 F 5k VREF REF SENSE IINA R1 0.1 F 10 F IINB COMMON MODE VOLTAGE 10 F 0.1 F QINB 0.1 F 0.1 F VREF I OR QREFB REFSENSE 0.1 F 10 F QINA R2 0.1 F I OR QREFB 0.1 F 10 F 0.1 F 1.5V 0.1 F 0.5V ANALOG INPUT 1k IINB 1.0 F 0.1 F IINA I OR QREFB 0.1 F I OR QREFT 0.1 F 10 F AD9281 VREF REFSENSE Figure 18. Example Configuration for 0.5 V-1.5 V ac Coupled Single-Ended Inputs Transformer Coupled Inputs AD9281 5k Another option for input ac coupling is to use a transformer. This not only provides dc rejection, but also allows truly differential drive of the AD9281's analog inputs, which will provide the optimal distortion performance. Figure 19 shows a recommended transformer input drive configuration. Resistors R1 and R2 define the termination impedance of the transformer coupling. The center tap of the transformer secondary is tied to the common-mode voltage, establishing the dc bias point for the analog inputs. AD9281 I OR QREFT Figure 17. Example Configuration for 0 V-1 V SingleEnded Input Signal Note that since the inputs are high impedance, this reference level can easily be generated with an external resistive divider with large resistance values (to minimize power dissipation). A decoupling capacitor is recommended on this input to minimize the high frequency noise-coupling onto this pin. Decoupling should occur close to the ADC. Differential Inputs Figure 19. Example Configuration for Transformer Coupled Inputs Use of differential input signals can provide greater flexibility in input ranges and bias points, as well as offering improvements in distortion performance, particularly for high frequency input signals. Users with differential input signals will probably want to take advantage of the differential input structure of the AD9281. Performance is still very good for single-ended inputs. Converting a single-ended input to a differential signal for application to the converter is probably only worth considering for very high frequency input signals. AC-Coupled Inputs Crosstalk: The internal layout of the AD9281, as well as its pinout, was configured to minimize the crosstalk between the two input signals. Users wishing to minimize high frequency crosstalk should take care to provide the best possible decoupling for input pins (see Figure 20). R and C values will make a pole dependant on antialiasing requirements. Decoupling is also required on reference pins and power supplies (see Figure 21). IINA QINA AD9281 IINB QINB If the signal of interest has no dc component, ac coupling can be easily used to define an optimum bias point. Figure 18 illustrates one recommended configuration. The voltage chosen for the dc bias point (in this case the 1 V reference) is applied to both IINA and IINB pins through 1 k resistors (R1 and R2). IINA is coupled to the input signal through Capacitor C1, while IINB is decoupled to ground through Capacitor C2. Figure 20. Input Loading V ANALOG AVDD 10 F 0.1 F DVDD 0.1 F 10 F V DIGITAL AD9281 I OR QREFT 0.1 F I OR QREFB 10 F 0.1 F 0.1 F Figure 21. Reference and Power Supply Decoupling REV. E -9- AD9281 REFERENCE AND REFERENCE BUFFER The reference and buffer circuitry on the AD9281 is configured for maximum convenience and flexibility. An illustration of the equivalent reference circuit is show in Figure 26. The user can select from five different reference modes through appropriate pin-strapping (see Table I below). These pin strapping options cause the internal circuitry to reconfigure itself for the appropriate operating mode. Table I. Table of Modes Externally Set Voltage Mode (Figure 24)--this mode uses the on-chip reference, but scales the exact reference level though the use of an external resistor divider network. VREF is wired to the top of the network, with the REFSENSE wired to the tap point in the resistor divider. The reference level (and input full scale) will be equal to 1 V x (R1 + R2)/R1. This method can be used for voltage levels from 0.7 V to 2.5 V. 1F 0.1 F - + 5k 1V VREF +- Mode 1V 2V Programmable External Input Span 1V 2V 1 + (R1/R2) = External Ref REFSENSE Pin Figure VREF AGND See Figure AVDD 22 23 24 25 R2 R1 REFSENSE AD9281 AVSS I OR QREFT 0.1 F I OR QREFB 0.1 F 10 F 0.1 F 1 V Mode (Figure 22)--provides a 1 V reference and 1 V input full scale. Recommended for applications wishing to optimize high frequency performance, or any circuit on a supply voltage of less than 4 V. The part is placed in this mode by shorting the REFSENSE pin to the VREF pin. 1V 0V IINA 5k IINB 10 F 0.1 F 5k 1V QINB QINA 1V 0V VREF = 1 + R2 R1 Figure 24. Programmable Reference External Reference Mode (Figure 25)--in this mode, the onchip reference is disabled, and an external reference applied to the VREF pin. This mode is achieved by tying the REFSENSE pin to AVDD. 1V 0V IINA QINA QINB 5k IINB 10 F 0.1 F 1V 0V AD9281 VREF REFSENSE I OR QREFT 0.1 F 0.1 F I OR QREFB 0.1 F 10 F 10 F 0.1 F 1V EXT REFERENCE 10 F AD9281 VREF I OR QREFT 0.1 F 0.1 F I OR QREFB 10 F 0.1 F 0.1 F Figure 22. 0 V to 1 V Input AVDD REFSENSE 2 V Mode (Figure 23)--provides a 2 V reference and 2 V input full scale. Recommended for noise sensitive applications on 5 V supplies. The part is placed in 2 V reference mode by grounding (shorting to AVSS) the REFSENSE pin. 2V 0V IINA 5k IINB 10 F 0.1 F 5k QINB QINA 2V 0V Figure 25. External Reference AD9281 VREF I OR QREFT 0.1 F 0.1 F I OR QREFB REFSENSE 0.1 F 10 F Reference Buffer--The reference buffer structure takes the voltage on the VREF pin and level-shifts and buffers it for use by various sub-blocks within the two A/D converters. The two converters share the same reference buffer amplifier to maintain the best possible gain match between the two converters. In the interests of minimizing high frequency crosstalk, the buffered references for the two converters are separately decoupled on the IREFB, IREFT, QREFB and QREFT pins, as illustrated in Figure 26. 10 F 0.1 F Figure 23. 0 V to 2 V Input -10- REV. E AD9281 ADC CORE 0.1 F 10 F 0.1 F 1.0 F IREFT 0.1 F IREFB VREF 0.1 F REFSENSE INTERNAL CONTROL LOGIC 10k 1V QREFT 0.1 F QREFB 0.1 F 10 F 0.1 F feature chip capacitors located close to the converter IC. The capacitors are connected to either IREFT/IREFB or QREFT/ QREFB. A connection to both sides is not required. COMMON-MODE PERFORMANCE Attention to the common-mode point of the analog input voltage can improve the performance of the AD9281. Figure 27 illustrates THD as a function of common-mode voltage (center point of the analog input span) and power supply. Inspection of the curves will yield the following conclusions: 1. An AD9281 running with AVDD = 5 V is the easiest to drive. 2. Differential inputs are the most insensitive to common-mode voltage. 3. An AD9281 powered by AVDD = 3 V and a single ended input, should have a 1 V span with a common-mode voltage of 0.75 V. 10k AVSS AD9281 Figure 26. Reference Buffer Equivalent Circuit and External Decoupling Recommendation For best results in both noise suppression and robustness against crosstalk, the 4-capacitor buffer decoupling arrangement shown in Figure 26 is recommended. This decoupling should -3 -15 -13 -23 THD - dB -33 2V -43 -53 1V -63 -73 -0.5 -55 THD - dB -25 2V -35 -45 1V 0 0.5 CML - V 1 1.5 -65 -0.5 0 0.5 CML - V 1 1.5 a. Differential Input, 3 V Supplies c. Single-Ended Input, 3 V Supplies -35 -15 -40 -45 THD - dB -50 -55 1V -60 -65 -70 -0.5 -55 2V THD - dB -25 -35 2V 1V -45 0 0.5 1 CML - V 1.5 2 2.5 -65 -0.5 0 0.5 1 CML - V 1.5 2 2.5 b. Differential Input, 5 V Supplies d. Single-Ended Input, 5 V Supplies Figure 27. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz) REV. E -11- AD9281 DIGITAL INPUTS AND OUTPUTS SELECT Each of the AD9281 digital control inputs, CHIP SELECT, CLOCK, SELECT and SLEEP are referenced to AVDD and AVSS. Switching thresholds will be AVDD/2. The format of the digital output is straight binary. A low power mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD9281 will drop below 22 mW. CLOCK INPUT When the select pin is held LOW, the output word will present the "Q" level. When the select pin is held HIGH, the "I" level will be presented to the output word (see Figure 1). The AD9281's select and clock pins may be driven by a common signal source. The data will change in 5 ns to 11 ns after the edges of the input pulse. The user must make sure the interface latches have sufficient hold time for the AD9281's delays (see Figure 28). CLOCK CLOCK SOURCE I LATCH SELECT CLK DATA OUT DATA Q LATCH CLOCK Q PROCESSING DATA I PROCESSING The AD9281 clock input is internally buffered with an inverter powered from the AVDD pin. This feature allows the AD9281 to accommodate either +5 V or +3.3 V CMOS logic input signal swings with the input threshold for the CLK pin nominally at AVDD/2. The pipelined architecture of the AD9281 operates on both rising and falling edges of the input clock. To minimize duty cycle variations the logic family recommended to drive the clock input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 28 MSPS operation. Running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD9281 at slower clock rates. The power dissipated by the output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. DIGITAL OUTPUTS Figure 28. Typical De-Mux Connection APPLICATIONS USING THE AD9281 FOR QAM DEMODULATION Each of the on-chip buffers for the AD9281 output bits (D0-D9) is powered from the DVDD supply pin, separate from AVDD. The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level. For DVDD = 5 V, the AD9281 output signal swing is compatible with both high speed CMOS and TTL logic families. For TTL, the AD9281 on-chip, output drivers were designed to support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 28 MSPS, other TTL families may be appropriate. For interfacing with lower voltage CMOS logic, the AD9281 sustains 28 MSPS operation with DVDD = 3 V. In all cases, check your logic family data sheets for compatibility with the AD9281's Specification table. A 2 ns reduction in output delays can be achieved by limiting the logic load to 5 pF per output line. THREE-STATE OUTPUTS QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in both FDMA as well as spread spectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency which is both modulated in amplitude (i.e., AM modulation) and in phase (i.e., PM modulation). At the transmitter, it can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. This results in an inphase (I) carrier component and a quadrature (Q) carrier component at a 90 phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier or IF frequency. Figure 29 shows a typical analog implementation of a QAM modulator using a dual 10-bit DAC with 2x interpolation, the AD9761. A QAM signal can also be synthesized in the digital domain thus requiring a single DAC to reconstruct the QAM signal. The AD9853 is an example of a complete (i.e., DAC included) digital QAM modulator. IOUT DSP OR ASIC 10 AD9761 QOUT CARRIER FREQUENCY 0 90 TO MIXER The digital outputs of the AD9281 can be placed in a high impedance state by setting the CHIP SELECT pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. NYQUIST FILTERS QUADRATURE MODULATOR Figure 29. Typical Analog QAM Modulator Architecture -12- REV. E AD9281 At the receiver, the demodulation of a QAM signal back into its separate I and Q components is essentially the modulation process explain above but in the reverse order. A common and traditional implementation of a QAM demodulator is shown in Figure 30. In this example, the demodulation is performed in the analog domain using a dual, matched ADC and a quadrature demodulator to recover and digitize the I and Q baseband signals. The quadrature demodulator is typically a single IC containing two mixers and the appropriate circuitry to generate the necessary 90 phase shift between the I and Q mixers' local oscillators. Before being digitized by the ADCs, the mixed down baseband I and Q signals are filtered using matched analog filters. These filters, often referred to as Nyquist or PulseShaping filters, remove images-from the mixing process and any out-of-band. The characteristics of the matching Nyquist filters are well defined to provide optimum signal-to-noise (SNR) performance while minimizing intersymbol interference. The ADC's are typically simultaneously sampling their respective inputs at the QAM symbol rate or, most often, at a multiple of it if a digital filter follows the ADC. Oversampling and the use of digital filtering eases the implementation and complexity of the analog filter. It also allows for enhanced digital processing for both carrier and symbol recovery and tuning purposes. The use of a dual ADC such as the AD9281 ensures excellent gain, offset, and phase matching between the I and Q channels. AVDD A A DVDD D LOGIC SUPPLY ADC IC CSTRAY ANALOG CIRCUITS A CSTRAY DIGITAL CIRCUITS B IA ID DIGITAL LOGIC ICs VIN A AVSS A D = ANALOG = DIGITAL DVSS V GND A A D Figure 31. Ground and Power Consideration These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9281 in a solid ground plane. The power and ground return currents must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. Transients between AVSS and DVSS will seriously degrade performance of the ADC. I ADC DSP OR ASIC Q ADC DUAL MATCHED ADC NYQUIST FILTERS QUADRATURE DEMODULATOR CARRIER FREQUENCY FROM PREVIOUS STAGE LO 90C If the user cannot tie analog ground and digital ground together at the ADC, he should consider the configuration in Figure 32. Another input and ground technique is shown in Figure 32. A separate ground plane has been split for RF or hard to manage signals. These signals can be routed to the ADC differentially or single ended (i.e., both can either be connected to the driver or RF ground). The ADC will perform well with several hundred mV of noise or signals between the RF and ADC analog ground. Figure 30. Typical Analog QAM Demodulator GROUNDING AND LAYOUT RULES As is the case for any high performance device, proper grounding and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD9281 have been separated to optimize the management of return currents in a system. Grounds should be connected near the ADC. It is recommended that a printed circuit board (PCB) of at least four layers, employing a ground plane and power planes, be used with the AD9281. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. RF GROUND ANALOG GROUND DIGITAL GROUND ADC AIN BIN DATA LOGIC Figure 32. RF Ground Scheme REV. E -13- AD9281 EVALUATION BOARD The AD9281 evaluation board is shipped "ready to run." Power and signal generators should be connected as shown in Figure 33 Then the user can observe the performance of the Q channel. If the user wants to observe the I channel, then he +3V should install a jumper at JP22 Pins 1 and 2. If the user wants to toggle between I and Q channels, then a CMOS level pulse train should be applied to the "strobe" jack after appropriate jumper connections. +3V +5V AGND SYNTHESIZER 20MHz 2Vp-p SYNTHESIZER 1MHz 1Vp-p ANTIALIAS FILTER CLOCK AVDD DGND1 DVDD DGND2 DRVDD AD9281 Q IN P1 DSP EQUIPMENT Figure 33. Evaluation Board Connections -14- REV. E AD9281 - 9201EB - Figure 34. Evaluation Board Solder-Side Silkscreen +C5 C54 C4 +C36 C55 C35 C14 C17 C23 C27 R50 R51 C14 C50 C51 C20 C22 C52 C29 REV C24 R52 R53 C53 (NOT TO SCALE) (NOT TO SCALE) Figure 35. Evaluation Board Component-Side Layout REV. E -15- AD9281 (NOT TO SCALE) Figure 36. Evaluation Board Ground Plane Layout (NOT TO SCALE) Figure 37. Evaluation Board Solder-Side Layout -16- REV. E AD9281 I_IN STROBE AGND AVDD CLOCK DGND1 DVDD DGND2 DBVDD AGND AVDD J1 J5 BJ2 C42 C41 JP22 C33 BJ1 L2 + C40 J6 R38 C38 R39 BJ4 BJ3 L3 + C43 BJ6 L4 C48 BJ5 + C46 C47 JP17 JP16 C45 C44 R36 R37 R13 R11 JP3 T1 R1 V8 JP15 TP4 TP7 R31 JP21 R4 R33 JP19 P1 C7 RN1 R32 JP13 4 TP2 TP1 C15 + C2 4 JP14 + C25 V2 R18 R14 V4 C9 C19 R2 V1 JP20 C6 C13 RN2 DBVDD R35 R34 C34 R40 C1 JP2 JP1 JP7 C3 J3 JP9 JP10 T2 TP5 TP6 C10 C49 + C37 DGND JP12JP11 C31 + C21 R16 R17 R24 JP4 + C11 C8 C12 + L5 C30 R30 R23 TP3 AGND J4 R8 C32 V6 D1 R9 JP6 R6 R7 R10 JP5 C24 + Q_IN R12 V3 (NOT TO SCALE) Figure 38. Evaluation Board Component-Side Silkscreen (NOT TO SCALE) Figure 39. Evaluation Board Power Plane Layout REV. E -17- U1 16 B B B B B B B B VCCB NC1 OE GND1 DRVDD 74LVXC4245 DRVDD 1 JP19 2 3 HDR3 C7 0.1 F TP2 DCIN1 CON1 U2 STROBE C4 0.1 21 D0 20 18 17 16 14 24 C9 0.1 F 23 22 13 D1 D2 D3 D4 DUTDATA [0...9] DUTCLK SELECT D9 D8 D7 D6 9 8 D5 D4 D3 D2 REFT-Q 26 R52 10 1 JP6 2 AVDD 3 HDR3 C52 10pF C53 10pF 27 28 INB-Q INA-Q CHIP-SELECT D1 D0 DVDD DVSS C29 CAP_NP J6 BNC ADC_CLK 7 6 5 REFB-Q 4 3 10 D7 D6 D5 D4 D3 D2 D1 AVDD D0 R31 500 R32 POT_2k C33 0.1 F 1 JP15 2 3 HDR3 74AHC14DW 74AHC14DW 1 L5 FERRITE_BEAD C30 CAP_NP 11 D8 11 D4 DRVDD C13 0.1 F 12 D9 13 R13 1k DVDD 14 D[0...9] B D0 D1 D2 D3 D4 VCCB NC1 OE GND1 B AVDD DUTCLK R11 1k 15 SLEEP INA-1 INB-1 REFT-1 REFB-1 AVSS 16 R51 10 17 18 C14 0.1 F C51 10pF C15 CAP_P 20 R14 R-S TBD 21 REFSENSE VREF AVDD 22 23 C24 10_10V 24 C26 CAP_NP 25 C25 CAP_P JP9 JUMPER C27 0.1 F INA-Q 3 JP14 INB-Q 1 2 4 HDR4 R_VREF R35 R-S 1 DCINO 5 C36 10_6V3 C55 1000pF C35 0.1 F TP6 CON1 R53 10 C22 0.1k C23 0.1 F 3 1 JP4 2 C16 CAP_NP 19 C17 0.1 F JP7 JUMPER C50 10pF JP5 JUMPER R50 10 U4 3 JP21 2 1 HDR3 AVDD 3 JP22 2 1 HDR3 C5 10_6V3 C54 1000pF CLK0 20 19 B A A A A A A A A VCCA T/R GND2 GND3 74LVXC4245 5 4 3 6 7 8 9 10 1 2 11 12 U8F 1 JP20 3 2 HDR3 74AHC14DW U8E 10 13 12 BD0 BD1 BD2 BD3 BD4 BCLK0 1 JP17 2 3 HDR3 GND3 12 GND2 11 T/R 2 C6 0.1 F VCCA 1 DRVDD A 10 A 7 BD9 RN1A A 6 BD8 A 5 BD7 RESISTOR 7PACK A 4 P1 BD6 A 3 BD5 A 9 A 15 DVDD D5 D6 DGND D7 D8 L4 DRVDD FERRITE BEAD DRVDD D9 DRVDD DVDD 24 C2 0.1 F 22 13 1 JP13 2 INB-1 R_VREF R1 R-S TBD 3 4 HDR3 23 14 17 C47 CAP_NP C48 CAP_NP 14 1 RN1B 13 2 RN1C DPWRIN BJ5 1 BANA C46 10_10V BJ6 1 BANA INA-1 18 19 20 21 8 DPWRIN C43 10_10V C44 CAP_NP C45 CAP_NP L3 DVDD FERRITE BEAD DVDD AD9281 APWRIN AVDD BJ3 BANA 1 BJ4 BANA 1 BJ1 1 BANA AGND AVDD L2 FERRITE BEAD AVDD VCC BJ2 1 BANA J5 BNC C40 10_10V C41 CAP_NP C42 CAP_NP GND STROBE R37 R-S 49.9 J1 BNC CH1IN HDR3 JP3 2 3 T1 TRANSFORMER CT 4 3 2 6 1 1 R2 R-S 50 JP2 PS JP2 JUMPER TP1 JUMPER C1 0.1 F CON1 R4 R-S 100 J3 MIDSCALE_IN C3 10_6V3 1 MIDSCALE_I R6 5k R7 15k C8 CAP_NP AVDD VREF TP3 CON1 13 31 30 11 4 2 29 9 28 12 3 3 RN1D 76 4 11 26 RN1E 5 24 22 5 CLK 10 8 RN1F OUT 1 10 9 6 12 RN2A 33 20 1 14 25 18 RN2B 23 27 2 13 16 RN2C 21 32 3 12 14 RN2D 34 19 33 4 11 40 RN2E 17 39 5 10 36 RN2F 38 15 37 6 9 CON40 DRVDD C10 0.1 F Figure 40. Evaluation Board TESTCHIP R_VREF C19 10_10V C20 0.1k AVDD R18 R-S TBD DVDD C49 10_10V -18- AD9201/ AD9281 R8 5.49k ADJ_REF U3 R9 POT_10k AD822 +8 D1 R12 1.5k C11 10_6V3 C12 0.1k R10 R-S 10 DIODE_ZENER AVDD R16 5k R17 15k C21 CAP_NP 74AHC14DW U8D 9 8 ADJ_REF U6 R23 POT_10k AD822 +8 R30 1.5k C31 10_6V3 R24 R-S 22 C32 0.1 F 74AHC14DW AVDD J4 BNC U8A 2 3 U8B 4 HDR3 3 CHOIN 2 1 JP10 R34 R-S 50 T2 TRANSFORMER CT 4 3 2 6 1 PS JP12 JP11 TP4 CON1 1 JP16 R36 CLK0 2 3 R-S TBD HDR3 AVDD R38 R-S 50 R33 500 C38 0.1 F U8C 6 R39 R-S 50 74AHC14DW TP7 CON1 DUTCLK JUMPER C34 0.1 F JUMPER TP5 CON1 C37 10_6V3 R40 R-S 100 REV. E NOT TO SCALE AD9281 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 0.311 (7.9) 0.301 (7.64) 1 14 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.79) 0.066 (1.67) 0.212 (5.38) 0.205 (5.21) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 8 0.015 (0.38) SEATING 0.009 (0.229) 0 0.010 (0.25) PLANE 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) REV. E -19- PRINTED IN U.S.A. C3117e-0-8/99 |
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